Dual-channel binary-countdown medium access control in wireless network-on-chip

Modern System-on-Chip design uses a rapidly increasing number of processing units for advanced information processing. When moving towards a billion-transistor era, ever increasing complexity and density of embedded components exacerbate on-chip communication, which serves as the fabric to integrate these heterogeneous components and provide a communication mechanism among them. In order to bridge the widening gap between on-chip communication needs and projected SoC performance, we propose a selfconfigurable multihop wireless micronetwork, dubbed Wireless Network-on-Chip, to serve as on-chip data and control communication infrastructure for next-generation billion-transistor SoCs. We present application-specific system architecture design of WNoC with the focus on radio frequency infrastructure. We propose a synchronized and distributed medium access control protocol for WNoC to resolve contentions between RF nodes. Binary countdownbased contention resolution and hidden terminal elimination schemes increase throughput and network utilization. Our simulation results show that DBC-MAC can achieve a promising performance in terms of throughput, latency, and network configuration.